The present invention relates, in general, to an apparatus and method for speed up of address generation, and more particularly to a method and apparatus for speed up of repetitive operations of hardware that incorporates linear single instruction multiple data (LSIMD) processing elements.
Just about any man-made product needs to be inspected or tested to assure that it functions correctly. In the past, most testing was done by humans. Today most testing is done using computer controlled machines. In the last 15 years technology has advanced to the point where computer controlled visual inspection is simple enough to be used in almost any manufacturing process. Still, one of the major factors limiting the use of electronic vision inspection is that most inspection systems take too much time to do an inspection. A visual inspection system that slows down an assembly line is one that typically will not be used.
A particular process used by electronic vision inspection systems to evaluate a camera image is extremely computationally intensive. A camera is used to capture an image which is transferred to an electronic memory for storage. The camera converts an image of an object into dots called pixels. A typical camera image is square and contains 512 rows and 512 columns. Each row contains 512 pixels and each column contains 512 pixels. This 512 by 512 image contains 512 times 512 or 262,144 pixels. Electronic vision inspection systems run special algorithms on these pixels to determine if the object represented by the image passes or fails testing. Testing of an image is slow because of the complexity of the algorithms and the large number of pixels in an image. In an attempt to speed up testing, most visual inspection systems use hardware that operates on several pixels at once. Ideally, the system would operate on all of the pixels in the image at once, however, this is not practical for reasons of the system's physical size and cost.
Most high performance visual inspection systems are implemented using LSIMD type architectures. LSIMD stands for Linear Single Instruction, Multiple Data. In other words, a single instruction, in this case a vision processing instruction, is supplied to an array of data processors that are connected and operate in parallel. When an instruction source supplies an instruction to the LSIMD array, each of the data processors in the LSIMD array reads the instruction and does the operation required by the instruction to their own pixel. The Linear part of LSIMD implies that the Single Instruction, Multiple Data array is constructed from a number of data processors equal to either the number of pixels in a row or the number of pixels in a column. A LSIMD array for a 512 by 480 image would therefore contain either 512 or 480 data processors depending on the implementation. A visual inspection system containing a LSIMD architecture tests a 512 by 480 image by sweeping the LSIMD array across the image horizontally or vertically one row or column at a time. Each new row or column that is operated on by the LSIMD array is accompanied by an address. This address selects which row or column of the image the LSIMD is to operate on.
An LSIMD array executes instructions received from a host computer or other instruction source. Identical instructions are used to process pixels in each row or column of the image. Some vision algorithms require a group of instructions to be repeated several times for each row or column in the image. Calculating all these instructions and addresses is slow and keeps the instruction source quite busy. This severely limits the time available for the instruction source to do the final evaluation of the processed image.
Many techniques have been used to increase processing speed of vision processing systems, but most have dealt with special algorithms, limiting the sections of the image to be processed, or increasing the speed capability of the instruction source and LSIMD hardware. It is relatively easy to increase the operating speed of a specially designed LSIMD array. However, increasing the speed of the instruction source is difficult and beyond certain limits, impossible. Typically the instruction source is a standard microprocessor. A state-of-the-art LSIMD array can generally be designed to be faster than the fastest microprocessor.
There is a need for a hardware enhancement to LSIMD type architectures that enables the instruction source to send one copy of repeating instructions to the LSIMD array. This enhancement should allow specially designed LSIMD arrays to operate at the full speed capability while at the same time relaxing the performance requirements of the instruction source.